1. Field of Invention
The present invention relates to a semiconductor device structure and fabricating method thereof. More particularly, the present invention relates to a thin film transistor liquid crystal display (TFT-LCD) pixel structure and fabricating method thereof.
2. Description of Related Art
A thin film transistor liquid crystal display (TFT-LCD) is a type of display that comprises a thin film transistor array substrate, a color filter array substrate and a liquid crystal layer. The thin film transistor array substrate includes a plurality of thin film transistors arranged to form an array and a plurality of pixel electrodes corresponding to the thin film transistors. Each thin film transistor has a gate, a channel layer, a drain terminal and a source terminal. The thin film transistor actually serves as a switching element in each liquid crystal display unit.
The operating principles of a thin film transistor are very similar to a conventional MOS device. Both the thin film transistor and the MOS device have three terminals (a gate terminal, a drain terminal and a source terminal). According to the fabricating material, a thin film transistor can be categorized as an amorphous silicon transistor or a polysilicon transistor. Since the amorphous silicon transistor has been around for some time, the fabricating technique is relatively mature. The fabrication of an amorphous silicon transistor typically involves forming a gate, a channel layer, source/drain terminals, a pixel electrode and a passivation layer over a substrate. Although amorphous silicon transistor has been developed for some time, researchers are still actively looking for innovative steps that can reduce the number of masking steps and increase production yield.
FIGS. 1A to 1E are schematic cross-sectional views showing the progression of steps for producing the pixel of a conventional thin film transistor liquid crystal display. The fabrication process includes five masking steps. First, as shown in FIG. 1A, a metallic layer is formed over a substrate 100. A first masking step is performed to pattern out a gate 102. Thereafter, insulation material is deposited over the substrate 100 globally to form an insulation layer 104 that covers the gate 102. That portion of the insulation layer 104 covering the gate 102 serves as a gate insulation layer.
As shown in FIG. 1B, an amorphous silicon layer (not shown) is formed over the insulation layer 104. A second masking step is performed to pattern out a channel layer 106. The channel layer 106 is formed over the gate insulation layer 104 above the gate 102. An ohmic contact layer (not shown) may also be formed over the channel layer 106.
As shown in FIG. 1C, another metallic layer (not shown) is formed over the substrate 100. A third masking step is carried out to pattern the metallic layer into source/drain terminals 108b/108a. In this step, a definite thickness of the channel layer 106 is also removed.
As shown in FIG. 1D, a passivation layer 110 is formed over the source/drain terminals 108b/108a. A fourth masking step is carried out to pattern the passivation layer 110. Thus, an opening 112 that exposes the drain terminal 108a is formed in the passivation layer 110.
Finally, as shown in FIG. 1E, an indium-tin oxide electrode layer is formed over the passivation layer 110 and inside the opening 112. A fifth masking step is carried out to pattern the indium-tin oxide layer into a pixel electrode 114. The pixel electrode 114 and the drain terminal 108a are electrically connected through conductive material within the opening 112.
In the aforementioned process of fabricating a TFT-LCD, altogether five masking steps are required. Since each masking step involves a series of sub-steps including moisture-release baking, coating, photoresist depositing, soft baking, photo-exposure, post-exposure baking, chemical development, hard baking and etching, each additional masking step will increase production cost considerably. Moreover, each additional sub-step carried out in the masking operation such as a moisture-release baking or coating will lower overall product yield.